1. Field of the Invention
The present invention relates to a test method for a storage device, and more specifically to, for example, a memory test circuit capable of reducing the number of scan flip-flop for fetching a test result, as a memory test circuit incorporated into the inside of a chip like a BIST circuit for RAM, thereby reducing the area of the test circuit.
2. Description of the Related Art
Recently, with an increasing number of loaded memory units into an LSI chip and a larger capacity of memory itself, a memory testing time increases, and a test cost has soared.
Therefore, a test method referred to as a “built-in self-test (BIST)” in which a test pattern is generated in the LSI chip is often used in a test of memory such as random access memory (RAM). Using the BIST, the time taken by inputting/outputting test data between an LSI tester and an LSI chip can be reduced, thereby shortening the testing time.
FIG. 1A shows the configuration of the memory test circuit in the BIST method according to the first conventional technology. FIG. 1A only shows the test circuit on the output side of the memory. Practically, there also is a test pattern generation circuit for generating an input test pattern for the memory on the memory input side, In FIG. 1A, for three RAM 100a, 100b, and 100c, there are signature analyzers 102a, 102b, and 102c for receiving the respective output of expected value generation units 101a, 101b, and 101c for generating an expected value for each bit output, together with the output of the above-mentioned RAM.
In the conventional technology, for example, each output of four bits of the RAM 100a is input to the four EXOR gates in the signature analyzer 102a together with the expected value of each bit output by the expected value generation unit 101a, and an exclusive logical sum of two inputs is obtained. If the output of the RAM and the expected value match each other, then “0” is output. If they do not match, then “1” is output from each EXOR gate. The output of each EXOR gate is input to the scan flip-flop (SFF), and the value of the signature of the RAM as output of each EXOR gate is fetched to each SFF and stored there. The scan flip-flop is obtained by adding the functions of a scan shift to a common flip-flop, but the configuration itself of the SFF is not directly related to the present invention, and the detailed explanation of the configuration is omitted here.
In the first conventional technology, the SFF holding the value of the signature is required for each of the four bits of the RAM 100a, the two bits of the RAM 100b, and the two bits of the RAM 100c. In this example, a total of eight SFFs are used.
FIG. 1B is a time chart of the shipment test of the RAM according to the first conventional technology. In the first conventional technology, since an SFF is provided for each bit of the three RAM 100a, 100b, and 100c, the shipment test can be simultaneously performed on the three RAM units.
Since the SFF is provided for each bit of the RAM as described above in the first conventional technology shown in FIG. 1A, there are advantages that all tests on the RAM can be simultaneously performed at the shipment test and in the defect analysis for determining the fault of a bit of any RAM, and a necessary test cost is low. However, it also has the disadvantage that since a number of SFFs having large areas as compared with other cells are used, the overhead of the areas is large.
To reduce the overhead of the areas, there are some methods of sharing an SFF in the conventional technologies. FIG. 1C shows the configuration of the circuit according to the second conventional technology, and FIG. 1D shows the configuration of the circuit according to the third conventional technology. In the second conventional technology shown in FIG. 1C, the value of the signature corresponding to the output of each RAM is collected by the OR gate, and provided for one SFF.
In the third embodiment shown in FIG. 1D, the signature for the output of each bit of a plurality of RAM is collected by one OR gate, and input to one SFF. In these second and third conventional technologies, the value of the signature as a nonmatching detection signal indicating a result of nonmatching with the expected value is “1”, and it is determined that although the OR gate collects the value, any RAM or any bit is defective. Relating to sharing an SFF using the above-mentioned OR gate, a similar circuit is disclosed by the patent documents 1 through 3.                [Patent Document 1] Japanese Patent Application Publication No. 2002-163899 “Semiconductor Storage Device”        [Patent Document 2] Japanese Patent Publication No. 2974313 “BIST Circuit and Semiconductor Integrated Circuit”        [Patent Document 3] Japanese Patent Publication No. 3193622 “BIST Tester for Multiple Memory Units”        
According to the second and third conventional technologies, there are the advantages that the number of SFFs is reduced and the overhead of the areas decreases, that at the shipment test which is carried out to detect a defect in any RAM or bit, a plurality of RAM can be simultaneously tested as shown in FIG. 1B for the first conventional technology, and that the test cost is small. On the other hand, there is the disadvantage that a defect for each bit or a defect for each RAM cannot be discriminated, thereby failing in performing a defect analysis.
As another method of sharing an SFF, there is a sharing method for reducing the number of SFFs using a selector. FIG. 1E shows the configuration of the circuit according to the fourth conventional technology. FIG. 1G shows the configuration of the circuit according to the fifth conventional technology. In FIG. 1E, the output of each RAMs is selected by a selector in a bit unit. The selection result is compared with the expected value output by an expected value generation unit. and the output of the EXOR gate as a comparison result is provided for each SFF.
FIG. 1F is a time chart of a shipment test of the RAM according to the fourth conventional technology shown in FIG. 1E. In the fourth conventional technology, for example, in the four output bits of the RAM 100a, the first and third bits are first selected and tested, and after the test, the second and fourth bits are selected and tested. Therefore, for example, the testing time is double the time according to the first conventional technology shown in FIG. 1B.
In the fifth conventional technology shown in FIG. 1G, an output bit signal is selected, from a plurality of RAM, that is, from the two RAM units (RAMs, for short, hereinafter) in this example, thereby reducing the number of SFFs. FIG. 1H is a time chart of the test at the shipment of RAM in the fifth conventional technology. First, the four bit RAM 100a is tested. After the test, the tests of the RAM 100b and the RAM 100c are simultaneously performed. Like the fourth and fifth conventional technologies, a method using a selector is disclosed by the patent documents 4 and 5.                [Patent Document 4] Japanese Patent Application Publication No. 2003-346498 “BIST Circuit”        [Patent Document 5] Japanese Patent Application Publication No. 2004-144717 “RAM Test Circuit”        
In the above-mentioned fourth and fifth conventional technologies, in addition to the number of SFFs, the number of EXOR gates can be reduced. Therefore, there is the merit of reducing the overhead of the areas. However, it is necessary to add a selector. Also at the shipment test on the RAM, all bits of RAM cannot be simultaneously tested in the fourth conventional technology, and a plurality of RAM cannot be simultaneously tested in the fifth conventional technology. Although a defect analysis itself can be performed, but since the output simultaneously observed is limited, it takes a long time to make an analysis. However, a defect analysis is not to test a large number of chips as in the shipment test. Therefore, it does not badly affect the necessary cost.
As described above, there have been the problems with the conventional technologies that the number of SFFs and the overhead of the areas increase in reducing the cost of a defect analysis with all bits of a plurality of RAM in a defect analysis simultaneously observed, that the defect analysis cannot be made or a long testing time of the defect analysis is required or that a long testing time is also required in a shipment test, in reducing the number of SFFs and the overhead of the areas, etc.